This invention pertains to ferroelectric capacitors and integrated circuit memory devices, and, more particularly, to textured electrodes for ferroelectric capacitors.
The term “texture” or “textured” generally refers to the crystallographic orientation of the material being discussed, and is not to be confused with the surface smoothness of the material. Specifically, the texture of the electrode and dielectric material being discussed refers to the crystallographic orientation of the material in the “Z-axis” and does not generally describe the orientation of the material in the X or Y axes (parallel to the surface of the integrated circuit). In fact, the grain structure of the material is generally random in the X or Y axes, yet it is ordered in the preferred orientation in the Z-axis of the material for maximizing electrical performance as is disclosed in greater detail below with respect to the description of the invention.
One possibility for improving the electrical performance of a ferroelectric memory is by texturing the ferroelectric dielectric material. Referring now to FIG. 1, a typical prior art ferroelectric capacitor 10 is shown including a substrate 12, a bottom electrode 14, a Perovskite ferroelectric dielectric layer 16 such as Pb(Zr1−XTiX)O3 (“PZT”), and a top electrode 18. The bottom electrode layer 14 and top electrode layer 18 are typically platinum or iridium. It is desirable for ferroelectric dielectric layer 16 to have a texture that maximizes electrical performance, and not a random grain structure. The use of a textured dielectric layer helps to maximize signal strengths and minimize operating voltage distribution since the polarization vector of all of the grains in the layer are oriented in the same direction. This is especially important if, as is required in integrated circuit memories, the capacitor area is very small (<1 μm2) and the number of grains is also small (<50 grains). Randomly distributed grain orientation in the Z-axis of the dielectric film substantially affects signal strength and electrical memory performance.
Presently available bottom electrode structures and processing methods do not support a textured PZT ferroelectric dielectric layer and therefore process control and narrow single-bit signal distributions cannot be achieved for high density memories. With randomly oriented materials, the distribution in bit signals is large for capacitor sizes approaching the grain size of the PZT layer (typically 0.1-0.3 μm) since the switchable polarization is a vector property linked with specific crystal directions.
In particular, it has also been found that it is difficult to maintain good PZT crystallographic texture on iridium metal bottom electrodes. Iridium metal is oxidized when it is exposed to air or oxygen-containing environments. Currently, after iridium deposition, the iridium is typically exposed to air, resulting in a surface layer of IrOX that does not provide the proper template for textured PZT growth. While it may be possible to prevent iridium oxidation by directly depositing the PZT after iridium deposition and avoiding a vacuum break, the oxygen present in the PZT and the atmosphere used to deposit PZT can also cause iridium oxidation in an uncontrolled manner.
Exposure, therefore, of an iridium bottom electrode to atmosphere causes surface oxidation of the iridium. This surface oxidation causes an undesirable non-oriented PZT dielectric layer to be formed. Current platinum technology does not prevent oxygen diffusion through the bottom electrode. This, in turn, does not allow protection of contacts that lie below the bottom electrode in a capacitor-on-plug FRAM® memory architecture.
What is desired, therefore, is a bottom electrode structure for a ferroelectric capacitor that supports the growth of a properly textured ferroelectric dielectric film.